US 12,470,726 B2
Validation framework for media encode systems
Karteek Renangi, Folsom, CA (US); Syed Ahsan, Folsom, CA (US); and Dmitry Ryzhov, Mountain View, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 14, 2021, as Appl. No. 17/644,253.
Prior Publication US 2022/0109825 A1, Apr. 7, 2022
Int. Cl. H04N 19/42 (2014.01)
CPC H04N 19/42 (2014.11) 17 Claims
OG exemplary drawing
 
1. A system comprising:
memory;
computer-executable instructions; and
processor circuitry to be programmed based on the computer-executable instructions to:
generate, with a video encoder simulation model, a first set of video encoding parameters;
train the video encoder simulation model based on the first set of video encoding parameters;
generate, with the video encoder simulation model, a second set of video encoding parameters;
provide the second set of video encoding parameters to an encoder device;
generate, with the video encoder simulation model, a first output representative of first encoded video content based on the second set of video encoding parameters;
obtain a second output representative of second encoded video content from the encoder device, the second output based on the second set of video encoding parameters;
perform a validation of the encoder device based on the first output and the second output;
generate, with the video encoder simulation model, a third output based on the first set of video encoding parameters;
compare the third output to a reference output, the reference output based on a first video codec;
determine that the third output and the reference output are different;
generate, with the video encoder simulation model, a fourth output based on the first set of video encoding parameters;
compare the fourth output to the reference output; and
determine that the fourth output corresponds to the reference output.