US 12,470,643 B2
Method and apparatus to perform operations on multiple segments of a data packet in a network interface controller
Naru Dames Sundar, Los Gatos, CA (US); and Chih-Jen Chang, Union City, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,089.
Prior Publication US 2022/0116487 A1, Apr. 14, 2022
Int. Cl. H04L 69/22 (2022.01)
CPC H04L 69/22 (2013.01) [H04L 2212/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device comprising:
a package comprising:
a stacked High Bandwidth Memory (HBM)-consistent memory; and
a network interface controller (NIC) communicatively coupled to the memory, the NIC comprising:
an ingress buffer;
a payload buffer circuitry;
a host interface; and
packet processing circuitry to:
inspect a first segment of a data packet to determine whether to stream a second segment of the data packet or to store the first segment and the second segment of the data packet in the memory to perform operations on the first segment and the second segment of the data packet, and based on a determination to stream the second segment of the data packet, the packet processing circuitry is to copy the second segment of the data packet from port circuitry via the ingress buffer and the payload buffer circuitry to the host interface.