US 12,470,489 B2
Methods and apparatus for performance scaling with parallel processing of sliding window management on multi-core architecture
Surekha Peri, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 18/003,267
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jul. 20, 2021, PCT No. PCT/US2021/042346
§ 371(c)(1), (2) Date Dec. 23, 2022,
PCT Pub. No. WO2022/020336, PCT Pub. Date Jan. 27, 2022.
Claims priority of provisional application 63/054,106, filed on Jul. 20, 2020.
Prior Publication US 2023/0300075 A1, Sep. 21, 2023
Int. Cl. H04L 47/22 (2022.01); H04L 47/50 (2022.01)
CPC H04L 47/225 (2013.01) [H04L 47/50 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one memory;
instructions in the apparatus; and
processor circuitry to be programmed based on the instructions to:
partition a packet flow into two or more sub flows based on a packet flow distribution configuration, the two or more sub flows associated respectively with two or more sliding windows that are able to slide in parallel;
update the two or more sliding windows with data included in the two or more sub flows;
slide the two or more sliding windows based on a window threshold being satisfied;
provide the two or more sub flows to a buffer to schedule distribution of the two or more sub flows;
dequeue the two or more sub flows from the buffer to one or more hardware cores; and
cause transmission of the two or more sub flows to a destination device.