US 12,470,361 B2
Active state power optimization for high-speed serial input/output interfaces
Per E. Fornberg, Portland, OR (US); Anoop Karunan, Bangalore (IN); Aruna Kumar L S, Bangalore (IN); Sunil Kumar CR, Bangalore (IN); and Sleiman Bou-Sleiman, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,339.
Prior Publication US 2022/0200780 A1, Jun. 23, 2022
Int. Cl. H04L 7/00 (2006.01); G06F 1/26 (2006.01); G06F 13/42 (2006.01)
CPC H04L 7/0091 (2013.01) [G06F 1/26 (2013.01); G06F 13/4282 (2013.01); H04L 7/0008 (2013.01); H04L 7/0079 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and
power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link, wherein, responsive to receiving the at least one margin measurement, the power adjustment circuitry is to determine, based on an expected change of power in the receiver circuitry, that overall power used to communicate over the serial communication link will be improved through adjusting the power level of the transmission circuitry.