US 12,470,319 B2
Low latency retimer and low latency control method
Yu Hong, Shanghai (CN); Shan Wang, Shanghai (CN); Ranran Fan, Shanghai (CN); Dan Wang, Shanghai (CN); and Zhongyuan Chang, Shanghai (CN)
Assigned to Montage Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed by Montage Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed on Sep. 22, 2022, as Appl. No. 17/950,140.
Claims priority of application No. 202111220992.5 (CN), filed on Oct. 20, 2021.
Prior Publication US 2023/0117385 A1, Apr. 20, 2023
Int. Cl. H04L 1/00 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC H04L 1/0018 (2013.01) [G06F 13/161 (2013.01); G06F 13/4291 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A low latency retimer, comprising two physical layer modules, wherein the physical layer modules comprise a first physical layer module is provided on a first side of a chip package of the retimer, and a second physical layer module provided on a second side of the chip package opposite to the first side, wherein each physical layer module comprises at least one set of signal transceiver units, wherein each set of the signal transceiver units comprises a signal receiving unit and a signal transmitting unit; for each set of the signal transceiver units:
the signal receiving unit performs a serial-to-parallel conversion on a first high-speed serial signal to generate a parallel signal and to send the parallel signal to the signal transmitting unit, and
the signal transmitting unit performs a parallel-to-serial conversion on the parallel signal to convert the parallel signal into a second high-speed serial signal, and output the second high-speed serial signal;
for each set of the signal transceiver units on the first side of chip package, the signal receiving unit has a first signal pin, and the signal transmitting unit has a second signal pin, one of the first signal pin and the second signal pin is connected to a first chip package pin on the first side of the chip package, and the other of the first signal pin and the second signal pin is connected to a second chip package pin on the second side of the chip package.