US 12,470,231 B2
Method and apparatus to perform cyclic redundancy check training in a memory module
Tonia M. Rose, Wendell, NC (US); and Saravanan Sethuraman, Bayan Lepas (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 7, 2022, as Appl. No. 17/688,125.
Prior Publication US 2022/0190844 A1, Jun. 16, 2022
Int. Cl. H03M 13/09 (2006.01); G06F 13/16 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/09 (2013.01) [G06F 13/1673 (2013.01); G06F 13/1684 (2013.01); H03M 13/611 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module comprising:
a hardware interface to interface with a command bus and a data bus having multiple data (DQ) signal lines and a CRC signal line, the hardware interface to receive a command on the command bus to trigger training of signaling on the multiple data (DQ) signal lines and the CRC signal line that includes testing and setting of electrical parameters or timing parameters that control respective data signal eyes for signaling on each of the multiple data (DO) signal lines and on the CRC signal line; and
a data buffer to include pattern generation and checking circuitry for each of the multiple data (DQ) signal lines and the CRC signal line to perform the training of signaling on the multiple data (DQ) signal lines and the CRC signal line, wherein the testing and setting of electrical parameters or timing parameters that control respective data signal eyes for the signaling on each of the multiple data (DO) signal lines and on the CRC signal line occurs without interfering with data stored in a memory integrated circuit.