US 12,470,222 B2
Digital duty cycle calibration
Dong-Young Chang, San Jose, CA (US); Steven Ernest Finn, Atlanta, GA (US); and Dominic Wingkin Yip, Fremont, CA (US)
Assigned to RENESAS ELECTRONICS AMERICA INC., Milpitas, CA (US)
Filed by RENESAS ELECTRONICS AMERICA INC., Milpitas, CA (US)
Filed on Nov. 21, 2023, as Appl. No. 18/516,084.
Prior Publication US 2025/0167788 A1, May 22, 2025
Int. Cl. H03L 7/08 (2006.01); H03K 3/017 (2006.01); H03K 5/01 (2006.01); H03K 5/00 (2006.01)
CPC H03L 7/08 (2013.01) [H03K 3/017 (2013.01); H03K 5/01 (2013.01); H03K 2005/00286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a processor;
a system duty cycle control (DCC) circuit configured to generate a clock signal; and
a circuit configured to:
perform a first phase shift on a clock signal to generate a first phase-shifted signal;
perform a second phase shift on the clock signal to generate a second phase-shifted signal;
perform a fixed DCC on the first phase-shifted signal to generate a first voltage signal;
sweep the second phase-shifted signal at a range of duty cycles to generate a second voltage signal; and
sample an output clock signal at a time in which the first voltage signal and the second voltage signal overlaps;
the processor being configured to generate a digital code based on the output clock signal, and
the system DCC circuit being configured to calibrate the clock signal using the digital code.