| CPC H03K 19/17728 (2013.01) [G06F 9/30134 (2013.01); G06F 9/4498 (2018.02); H03K 19/21 (2013.01)] | 19 Claims |

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1. A method of protecting an integrated circuit design against confidentiality and integrity attacks, the method comprising:
receiving, by a computing device, a file including data comprising a hardware netlist;
converting, by the computing device, the data into a hypergraph, wherein the hypergraph comprises (i) a plurality of nodes representative of a plurality of logic gates and (ii) one or more edges representative of one or more connections of the plurality of logic gates;
replacing, by the computing device, a node from the plurality of nodes in the hypergraph with a configurable lookup table (LUT);
inserting, by the computing device, a first programmable component into the hypergraph based on the configurable LUT, wherein the first programmable component comprises a programmable interconnect that is inserted at an output of the configurable LUT; and
generating, by the computing device, a redacted design output file based on the hypergraph including the configurable LUT and the first programmable component.
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