| CPC H03K 17/6872 (2013.01) [G02F 1/0121 (2013.01)] | 20 Claims |

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1. A device comprising:
a first differential pair of transistors having drain nodes coupled to a differential pair of combiner nodes, having source nodes coupled in common to a first tail current source, and having gate nodes coupled to output nodes of a pre-driver stage;
a first pair of cascode transistors having drain nodes, gate nodes coupled in common to a first cascode bias node, and source nodes coupled to the differential pair of combiner nodes, the first pair of cascode transistors having a first breakdown voltage;
a second pair of cascode transistors having drain nodes, source nodes coupled to the drain nodes of the first pair of cascode transistors, and gate nodes coupled in common to a second cascode bias node, the second pair of cascode transistors having a second breakdown voltage, wherein the second breakdown voltage is higher than the first breakdown voltage; and
an output network coupled to the drain nodes of the second pair of cascode transistors.
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