US 12,470,205 B2
Driving buffer with configurable slew rate for data transmission
Huan-Neng Chen, Taichung (TW); Chang-Fen Hu, Hsinchu (TW); and Shao-Yu Li, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 11, 2024, as Appl. No. 18/632,381.
Application 18/632,381 is a continuation of application No. 17/538,154, filed on Nov. 30, 2021, granted, now 11,967,958.
Claims priority of provisional application 63/182,007, filed on Apr. 30, 2021.
Prior Publication US 2024/0259004 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 5/01 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/01 (2013.01) [H03K 19/20 (2013.01); H03K 2005/00013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A driving buffer, comprising:
an input configured to receive an input signal with a rising edge or falling edge of digital data;
an output; and
a plurality of delay paths, each connected between the input and the output and being configured to delay the input signal by a respective amount of time and including a driver having a respective gain, at least two of the delay paths being configured to delay the input signals by different amounts of time from each other, wherein:
each of the plurality of delay paths includes: a delay cell having an input and an output and comprising a plurality of logic gates connected in series between the input and output of the delay cell, each of the plurality of logic gates having a respective input and output, the input of the delay cell being connected to the input of the driving buffer, and
the driver in each delay path has an input and an output, the input of the driver being selectably connected to the output one of the plurality of logic gates, and the output of the driver being connected to the output of the driving buffer.