| CPC H03H 11/04 (2013.01) [H02J 7/0047 (2013.01)] | 12 Claims |
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1. A noise reduction circuit comprising:
a first circuit including at least one resistance element and a first capacitor, and connected to a first sub-circuit including an analog-to-digital converter, the analog-to-digital converter including a first general-purpose input/output (GPIO) and a second GPIO, both the first and second GPIO including ports configured to communicate with components external to the analog-to-digital converter; and
a second circuit including a second capacitor connected in parallel with the first capacitor and a switch positioned between the second capacitor and a ground, the second circuit being connected in parallel with the first capacitor and connected to the first sub-circuit through the second GPIO,
wherein the second circuit is activated or deactivated according to control of the first sub-circuit, so that a noise cutoff frequency generated by the first circuit and the second circuit is adjusted,
wherein, when the second circuit is activated, a total capacitor capacity is a sum of a capacitance of the first capacitor and a capacitance of the second capacitor,
wherein the noise cutoff frequency is determined based on the total capacitor capacity,
wherein the first capacitor is directly connected to the ground,
wherein the first GPIO is configured to receive an input from the at least one resistance element and the first capacitor,
wherein the second GPIO is configured to output an activation or deactivation signal to the switch, and
wherein the output by the second GPIO does not loop back to the first GPIO through the second circuit.
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