US 12,470,180 B2
Common-gate amplifier circuit
Paolo Valerio Testa, Madrid (ES); and Shafiullah Syed, Murphy, TX (US)
Assigned to GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed by GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed on Jul. 14, 2022, as Appl. No. 17/864,733.
Prior Publication US 2024/0022219 A1, Jan. 18, 2024
Int. Cl. H03F 3/193 (2006.01); H10D 1/66 (2025.01)
CPC H03F 3/193 (2013.01) [H10D 1/66 (2025.01); H03F 2200/451 (2013.01); H03F 2200/72 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A structure comprising:
at least one well in a substrate;
a first metal layer connected to a gate of a transistor circuit;
a second metal layer overlapped over the first metal layer to form a first capacitor;
a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor;
a shallow trench isolation (STI) which separates a P+ region from an N+ region and separates the P+ region from the transistor circuit; and
at least one capacitance in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.