US 12,470,177 B2
Feedback topologies for amplifier gain reduction
Parvez Daruwalla, San Diego, CA (US); Rong Jiang, San Diego, CA (US); and Khushali Shah, San Diego, CA (US)
Assigned to PSEMI CORPORATION, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on May 27, 2022, as Appl. No. 17/804,470.
Prior Publication US 2023/0387863 A1, Nov. 30, 2023
Int. Cl. H03F 1/22 (2006.01); H03F 3/195 (2006.01); H03F 3/72 (2006.01)
CPC H03F 1/223 (2013.01) [H03F 3/195 (2013.01); H03F 3/72 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01); H03F 2203/7212 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A radio frequency (RF) amplifier comprising:
one or more transistors being serially connected, wherein a first transistor of the one or more transistors is configured to receive a first input signal from a first input terminal;
a first feedback path including a first programmable resistor coupling a drain terminal of a transistor of the one or more transistors to a source terminal of the first transistor of the one or more of transistors, and
a second feedback path including a second programmable resistor coupling a gate terminal of the first transistor to the source terminal of the first transistor.