US 12,470,045 B2
Semiconductor device with selective area epitaxy growth utilizing a mask to suppress or enhance growth at the edges
David Alexander Macquistan, Ottawa (CA); and Kelvin Prosyk, Luskville (CA)
Assigned to Ciena Corporation, Hanover, MD (US)
Filed by Ciena Corporation, Hanover, MD (US)
Filed on May 28, 2020, as Appl. No. 16/885,989.
Application 16/885,989 is a continuation in part of application No. 16/423,846, filed on May 28, 2019, granted, now 10,852,478.
Prior Publication US 2020/0381899 A1, Dec. 3, 2020
Int. Cl. H01S 5/32 (2006.01); H01L 21/02 (2006.01); H01S 5/10 (2021.01); H01S 5/22 (2006.01); H10F 71/00 (2025.01)
CPC H01S 5/3202 (2013.01) [H01L 21/02293 (2013.01); H01L 21/02392 (2013.01); H01S 5/1003 (2013.01); H01S 5/2206 (2013.01); H10F 71/00 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method comprising:
with a semiconductor wafer having an orientation in a plane, depositing a mask to the semiconductor wafer, wherein the mask is configured to cover a portion of the semiconductor wafer, and wherein the mask includes a perimeter having multiple sides such that most of the perimeter of the mask is substantially aligned along a preferred crystal direction relative to the orientation selected from approximately 34, 56, 124, 146, 214, 236, 304, or 326 degrees relative to a [011] crystallographic axis of the semiconductor wafer to specifically reduce growth enhancement at edges of the substantially aligned sides, wherein the preferred crystal direction is determined by forming circular mask islands at varying angular orientations relative to the [011] direction, measuring island heights and volumes resulting from Selective Area Epitaxy (SAE) growth, and correlating measured island heights and volumes to the angular orientations to identify angles providing reduced growth enhancement; and
performing Selective Area Epitaxy (SAE) growth on a surface of the semiconductor wafer.