US 12,469,954 B2
High precision scalable packaging architecture based on radio frequency scanning
Georgios Dogiamis, Chandler, AZ (US); Alon Cohen, Modiin Macabim Reut (IL); and Ophir Shabtay, Tzofit (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 22, 2022, as Appl. No. 17/700,819.
Prior Publication US 2023/0307846 A1, Sep. 28, 2023
Int. Cl. H01Q 1/22 (2006.01); H01Q 3/46 (2006.01); H01Q 15/14 (2006.01); H01Q 19/10 (2006.01); H01Q 21/08 (2006.01); H01L 23/498 (2006.01)
CPC H01Q 1/2283 (2013.01) [H01Q 3/46 (2013.01); H01Q 15/148 (2013.01); H01Q 19/104 (2013.01); H01Q 21/08 (2013.01); H01L 23/49827 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6677 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a plurality of transceiver modules, each transceiver module including a first antenna;
a printed circuit board (PCB); and
a reflector module coupled to the PCB and separated from the plurality of transceiver modules by a space, the reflector module comprising:
a substrate having a first side and an opposing second side, the first side being proximate to the plurality of transceiver modules,
an antenna array on the first side of the substrate, the antenna array including a plurality of second antennas; and
a first integrated circuit (IC) die and a second IC die on the second side of the substrate,
wherein:
the PCB is coupled to the reflector module on the second side of the substrate,
the second antennas are coupled to the first IC die by at least one of wired connections and wireless connections in the substrate,
the first IC die is coupled to the second IC die by conductive traces in the substrate, and transistors in the first IC die are larger than transistors in the second IC die.