US 12,469,835 B2
Semiconductor device
Yoshihiro Masumura, Tokyo (JP); Takamichi Hosokawa, Tokyo (JP); and Keita Takada, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Apr. 20, 2023, as Appl. No. 18/303,902.
Claims priority of application No. 2022-094814 (JP), filed on Jun. 13, 2022.
Prior Publication US 2023/0402443 A1, Dec. 14, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H02M 1/08 (2006.01); H02M 7/00 (2006.01); H10D 86/85 (2025.01)
CPC H01L 25/18 (2013.01) [H01L 23/49575 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 25/50 (2013.01); H01L 23/3107 (2013.01); H01L 23/49513 (2013.01); H01L 24/92 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/0613 (2013.01); H01L 2224/06155 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48101 (2013.01); H01L 2224/48108 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48257 (2013.01); H01L 2224/49109 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H02M 1/08 (2013.01); H02M 7/003 (2013.01); H10D 86/85 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first chip mounting portion;
a second chip mounting portion;
a first semiconductor chip mounted on the first chip mounting portion;
a second semiconductor chip mounted on the second chip mounting portion;
a third semiconductor chip mounted on the second chip mounting portion, the third semiconductor chip including a first coil and a second coil; and
a sealing body sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion and the second chip mounting portion,
wherein the first coil and the second coil are magnetically coupled to each other,
wherein the first coil is electrically connected with a first circuit formed in the first semiconductor chip,
wherein the second coil is electrically connected with a second circuit formed in the second semiconductor chip,
wherein, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil,
wherein a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip, and
wherein an area of the second chip mounting portion is larger than an area of the first chip mounting portion.