US 12,469,826 B2
Semiconductor module
Tadahiko Sato, Kawasaki (JP); and Kenichiro Sato, Kawasaki (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Jul. 7, 2023, as Appl. No. 18/348,770.
Application 18/348,770 is a division of application No. 17/187,588, filed on Feb. 26, 2021, granted, now 11,742,333.
Claims priority of application No. 2020-057337 (JP), filed on Mar. 27, 2020.
Prior Publication US 2023/0352453 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 23/64 (2006.01); H01L 25/07 (2006.01)
CPC H01L 25/072 (2013.01) [H01L 23/49822 (2013.01); H01L 23/50 (2013.01); H01L 23/647 (2013.01); H01L 24/32 (2013.01); H01L 2224/32245 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor module, comprising:
a multilayer substrate having a main wiring layer formed therein, a main current flowing in the main wiring layer when the semiconductor module is turned on, the multilayer substrate further having another wiring layer;
a first semiconductor element and a second semiconductor element, each of which
has a top surface and a bottom surface that are opposite to each other,
has a top electrode disposed on the top surface thereof and a bottom electrode disposed on the bottom surface thereof, and
is disposed on the main wiring layer to which the bottom electrode is conductively connected;
a first metal plate having two end portions, one of the two end portions having a top surface and a bottom surface that are opposite to each other, the bottom surface being conductively connected to the top electrode of the first semiconductor element, the other one of the two end portions being connected to the another wiring layer via a bonding material;
a second metal plate having two end portions, one of the two end portions having a top surface and a bottom surface that are opposite to each other, the bottom surface being conductively connected to the top electrode of the second semiconductor element, the other one of the two end portions being connected to the another wiring layer via a bonding material;
a control board mounted only on the top surface of the one of the two end portions of the first metal plate; and
a chip resistor disposed on the control board, wherein
the control board includes
an insulating plate disposed on the top surface of the end portion, and
a control wiring layer for controlling turning on and off of the first and second semiconductor elements, and being disposed on the top surface of the insulating plate,
the first and second semiconductor elements each includes a gate electrode, and
the control wiring layer includes
a gate wiring member,
a gate wiring layer connected to the gate electrode of each of the first and second semiconductor elements through the gate wiring member,
an auxiliary wiring member, and
an auxiliary wiring layer connected to the top electrode of each of the first and second semiconductor elements through the auxiliary wiring member, the chip resistor being disposed on the auxiliary wiring layer.