US 12,469,823 B2
Repeater scheme for inter-die signals in multi-die package
Vijayakrishna J. Vankayala, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 12, 2022, as Appl. No. 17/887,372.
Claims priority of provisional application 63/348,384, filed on Jun. 2, 2022.
Prior Publication US 2023/0395566 A1, Dec. 7, 2023
Int. Cl. G11C 7/10 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 24/49 (2013.01); H01L 25/50 (2013.01); H01L 2224/49107 (2013.01); H01L 2224/4911 (2013.01); H01L 2224/49174 (2013.01); H01L 2224/49421 (2013.01); H01L 2924/1434 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system, comprising:
a host; and
a memory device comprising:
a plurality of memory dies, comprising:
a first memory die configured to handle interfacing for the memory device with the host;
a second memory die coupled to and configured to communicate with the first memory die via a first inter-die connection, wherein the second memory die comprises a second multiplexer, a second memory die transmitter, and a second memory die receiver;
a third memory die coupled to and configured to communicate with the second memory die via a second inter-die connection, wherein the third memory die comprises a third multiplexer and a third memory die transmitter;
wherein:
for a first signal driven by the first memory die via a unidirectional line of the memory device, the first signal is provided to a first multiplexer of the first memory die and an output of the first multiplexer is provided as an input to a first memory die transmitter, wherein the first signal is transmitted by the first memory die transmitter and received by the second memory die receiver, wherein the first signal is provided by the second memory die to the third multiplexer of the third memory die to facilitate repetition of the first signal to remaining memory dies of the plurality of memory dies.