| CPC H01L 25/0657 (2013.01) [H01L 21/02118 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/29693 (2013.01); H01L 2224/73 (2013.01); H01L 2224/73103 (2013.01); H01L 2224/73204 (2013.01)] | 14 Claims |
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1. A semiconductor package, comprising:
a lower semiconductor chip;
a plurality of semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip;
a plurality of connection bumps between the lower semiconductor chip and a bottommost one of the plurality of semiconductor chips, and the plurality of connection bumps being between the plurality of semiconductor chips;
a protection layer that covers a lateral surface of each of the plurality of connection bumps; and
a mold layer on the lower semiconductor chip, the mold layer covering lateral surfaces of the plurality of semiconductor chips,
wherein the mold layer extends between the bottommost one of the plurality of semiconductor chips and the lower semiconductor chip, and the mold layer extends between the plurality of semiconductor chips,
wherein the protection layer is between the mold layer and the lateral surface of each of the plurality of connection bumps,
wherein each of the plurality of semiconductor chips has a top surface and a bottom surface that are opposite to each other in the first direction, and
the protection layer extends between the mold layer and the top surface of each of the plurality of semiconductor chips, and the protection layer extends between the mold layer and the bottom surface of each of the plurality of semiconductor chips.
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