US 12,469,819 B2
Semiconductor device and method of forming embedded wafer level chip scale packages
Yaojian Lin, Singapore (SG); Pandi C. Marimuthu, Singapore (SG); Il Kwon Shim, Singapore (SG); and Byung Joon Han, Singapore (SG)
Assigned to STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed by STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed on Sep. 29, 2022, as Appl. No. 17/936,714.
Application 15/615,693 is a division of application No. 14/070,509, filed on Nov. 2, 2013, granted, now 9,704,824, issued on Jul. 11, 2017.
Application 17/936,714 is a continuation of application No. 16/918,281, filed on Jul. 1, 2020, granted, now 11,488,933.
Application 16/918,281 is a continuation of application No. 15/615,693, filed on Jun. 6, 2017, granted, now 10,777,528, issued on Sep. 15, 2020.
Application 14/070,509 is a continuation in part of application No. 14/036,525, filed on Sep. 25, 2013, granted, now 9,721,862, issued on Aug. 1, 2017.
Claims priority of provisional application 61/748,742, filed on Jan. 3, 2013.
Prior Publication US 2023/0012958 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H10D 84/01 (2025.01); H10D 89/00 (2025.01)
CPC H01L 24/96 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 24/11 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); H10D 84/01 (2025.01); H10D 89/011 (2025.01); H10D 89/013 (2025.01); H10D 89/015 (2025.01); H01L 2224/04105 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/10157 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, comprising:
providing a semiconductor die formed in a base substrate material;
forming a notch in the base substrate material outside a footprint of the semiconductor die;
disposing the semiconductor die over a carrier with a surface of the semiconductor die physically contacting the carrier, wherein the notch is disposed between the carrier and the base substrate material;
depositing an encapsulant over and around the semiconductor die and into the notch between the base substrate material and carrier;
removing the semiconductor die from the carrier after depositing the encapsulant; and
forming a fan-in interconnect structure over the semiconductor die after removing the semiconductor die from the carrier.