US 12,469,815 B2
Semiconductor package
Satoshi Yoshida, Kanagawa (JP); Tatsunori Sakano, Tokyo (JP); and Ryohei Gejo, Kanagawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Kawasaki (JP); and Toshiba Electronic Devices & Storage Corporation, Kawasaki (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Feb. 14, 2023, as Appl. No. 18/168,795.
Claims priority of application No. 2022-127742 (JP), filed on Aug. 10, 2022.
Prior Publication US 2024/0055386 A1, Feb. 15, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/492 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 25/07 (2006.01)
CPC H01L 24/32 (2013.01) [H01L 23/492 (2013.01); H01L 23/498 (2013.01); H01L 23/5226 (2013.01); H01L 24/29 (2013.01); H01L 25/072 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/2918 (2013.01); H01L 2224/32245 (2013.01); H01L 2924/13055 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first conductive member;
a second conductive member;
a plurality of semiconductor devices provided between the first conductive member and the second conductive member, one of the plurality of semiconductor devices including a semiconductor member, a first electrode provided between the first conductive member and the semiconductor member, a first control electrode provided between the first conductive member and the semiconductor member, a second control electrode provided between the first conductive member and the semiconductor member, and a second electrode provided between the semiconductor member and the second conductive member, the first conductive member being electrically connected to the first electrode, the second conductive member being electrically connected to the second electrode, a direction from the second control electrode to the first control electrode crossing a first direction from the first conductive member to the second conductive member;
a wiring member including a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region, a direction from the first wiring layer to the second wiring layer and a direction from the first wiring layer to the third wiring layer being along the first direction, at least a part of the insulating region being located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer, a position of the second wiring layer in the first direction being between a position of the insulating region in the first direction and a position of the plurality of semiconductor devices in the first direction, the second wiring layer including a first connection region and a second connection region, the first connection region being electrically connected to the first wiring layer, the third wiring layer being electrically connected to the first conductive member;
a first connection member provided between the first connection region and the first control electrode, the first connection member electrically connecting the first connection region to the first control electrode; and
a second connection member provided between the second connection region and the second control electrode, the second connection member electrically connecting the second connection region to the second control electrode.