US 12,469,814 B2
Integrated circuit package and method of forming same
Yu-Sheng Lin, Zhubei (TW); Shu-Shen Yeh, Taoyuan (TW); Ming-Chih Yew, Hsinchu (TW); Chin-Hua Wang, New Taipei (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 24, 2022, as Appl. No. 17/664,689.
Prior Publication US 2023/0387063 A1, Nov. 30, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/32 (2013.01) [H01L 23/49833 (2013.01); H01L 24/27 (2013.01); H01L 25/0655 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/26155 (2013.01); H01L 2224/27013 (2013.01); H01L 2224/3201 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/35121 (2013.01); H01L 2924/37001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
a package substrate, the package substrate having a first side and a second side opposite to the first side;
a package component bonded to the first side of the package substrate, the package component comprising an interposer, a first integrated circuit die attached to a first side of the interposer, a second integrated circuit die attached to a first side of the interposer, and a die-to-die underfill region between the first integrated circuit die and the second integrated circuit die, wherein the die-to-die underfill region is free of another integrated circuit die;
a front-side warpage control structure attached to the first side of the package substrate, the front-side warpage control structure comprising a first disconnected structure and a second disconnected structure laterally separated from each other by a first gap, a first line parallel to a longitudinal axis of the die-to-die underfill region intersecting the first disconnected structure and the first integrated circuit die, a second line parallel to the longitudinal axis of the die-to-die underfill region intersecting the second disconnected structure and the second integrated circuit die, the longitudinal axis of the die-to-die underfill region extending through the first gap; and
a backside warpage control structure embedded in the package substrate from the second side of the package substrate, the backside warpage control structure comprising a third disconnected structure and a fourth disconnected structure laterally separated from each other, the third disconnected structure overlapping with a first end of the die-to-die underfill region in a plan view, the fourth disconnected structure overlapping with a second end of the die-to-die underfill region in the plan view.