US 12,469,812 B2
Method for manufacturing semiconductor package with connection structures including via groups
Chien-Hsun Chen, Zhutian Township (TW); Jiun Yi Wu, Zhongli (TW); Chien-Hsun Lee, Chu-tung Town (TW); and Chung-Shi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 19, 2022, as Appl. No. 18/068,088.
Application 17/170,268 is a division of application No. 16/157,426, filed on Oct. 11, 2018, granted, now 10,916,519, issued on Feb. 9, 2021.
Application 18/068,088 is a continuation of application No. 17/170,268, filed on Feb. 8, 2021, granted, now 11,532,587.
Claims priority of provisional application 62/682,637, filed on Jun. 8, 2018.
Prior Publication US 2023/0122816 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/10 (2006.01)
CPC H01L 24/25 (2013.01) [H01L 21/568 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/105 (2013.01); H01L 2224/214 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/25174 (2013.01); H01L 2224/25177 (2013.01); H01L 2224/82005 (2013.01); H01L 2224/82951 (2013.01); H01L 2225/1058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
an Under-Bump Metallurgy (UBM);
a top via underlying and electrically coupling to the UBM;
a first conductive pad underlying and electrically coupling to the top via;
a first via group underlying and contacting the first conductive pad, wherein the first via group comprises a first plurality of vias, and the first via group has a first contour area;
a second conductive pad underlying and electrically coupling to the first via group;
a second via group underlying and contacting the second conductive pad, wherein the second via group comprises a second plurality of vias, and the second via group has a second contour area overlapped by the first contour area; and
a die underlying the second via group, wherein the die comprises a discrete via electrically coupling to the second via group, and wherein the first contour area and the second contour area overlap the discrete via.