US 12,469,809 B2
Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods
Kyle K. Kirby, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 20, 2024, as Appl. No. 18/610,263.
Application 18/610,263 is a continuation of application No. 18/108,935, filed on Feb. 13, 2023, granted, now 11,942,444.
Application 18/108,935 is a continuation of application No. 17/236,425, filed on Apr. 21, 2021, granted, now 11,587,895, issued on Feb. 21, 2023.
Prior Publication US 2024/0222300 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80143 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
a dielectric layer formed over the semiconductor substrate, the dielectric layer having an upper surface; and
an interconnect structure disposed at least partially within the dielectric layer, the interconnect structure including:
a conductive element electrically coupled to circuitry in the semiconductor substrate, the conductive element having an end surface, and
a perimeter structure of an insulating material surrounding the conductive element, an uppermost surface of the perimeter structure being vertically offset from the end surface of the conductive element and/or the upper surface of the dielectric layer.