| CPC H01L 23/562 (2013.01) [H01L 23/564 (2013.01); H01L 23/585 (2013.01)] | 7 Claims |

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1. A three-dimensional (3D) memory device comprising a chip region and a seal region surrounding the chip region, wherein the chip region comprises a chip array, and the seal region comprises a seal structure comprising:
a ring-shaped stack structure disposed on a substrate and surrounding the chip array; and
a dummy channel pillar array penetrating through the ring-shaped stack structure and comprising:
a first dummy channel pillar group comprising first dummy channel pillars arranged in a first direction and a second direction crossing the first direction to surround the chip array; and
a second dummy channel pillar group surrounding the first dummy channel pillar group and comprising second dummy channel pillars arranged in the first and second directions to surround the chip array,
wherein the first dummy channel pillars and the second dummy channel pillars are staggered with each other in the first and second directions, and the first dummy channel pillars are arranged between the two neighboring second dummy channel pillars when viewing from the first and second directions.
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