US 12,469,798 B2
Layout to reduce noise in semiconductor devices
Chih-Chang Cheng, Hsinchu (TW); Fu-Yu Chu, Hsinchu (TW); and Ruey-Hsin Liu, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 2, 2023, as Appl. No. 18/363,966.
Application 18/363,966 is a continuation of application No. 17/388,437, filed on Jul. 29, 2021, granted, now 11,817,396.
Application 17/388,437 is a continuation of application No. 16/924,627, filed on Jul. 9, 2020, granted, now 11,088,085, issued on Aug. 10, 2021.
Application 16/924,627 is a continuation of application No. 16/363,114, filed on Mar. 25, 2019, granted, now 10,714,432, issued on Jul. 14, 2020.
Prior Publication US 2023/0378090 A1, Nov. 23, 2023
Int. Cl. H01L 21/28 (2025.01); H01L 21/285 (2006.01); H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 23/552 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01)
CPC H01L 23/552 (2013.01) [H01L 21/28518 (2013.01); H01L 21/762 (2013.01); H10D 30/021 (2025.01); H10D 30/60 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an isolation structure in a semiconductor substrate and demarcating a device region of the semiconductor substrate;
a first source/drain region in the device region;
a second source/drain region in the device region and spaced from the first source/drain region in a direction; and
a gate overlying the device region and between and bordering the first source/drain region and the second source/drain region,
wherein the gate has a maximum width less than a maximum width of the first source/drain region, wherein the maximum width of the gate extends laterally transverse to the direction, and wherein the maximum width of the first source/drain region extends laterally transverse to the direction from a first sidewall of the isolation structure to a second sidewall of the isolation structure that faces the first sidewall of the isolation structure.