US 12,469,795 B2
Substrate structure including embedded semiconductor device and method of manufacturing the same
Chien-Fan Chen, Kaohsiung (TW); and Yu-Ju Liao, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on May 17, 2022, as Appl. No. 17/746,790.
Application 17/746,790 is a continuation of application No. 16/814,704, filed on Mar. 10, 2020, granted, now 11,335,646.
Prior Publication US 2022/0278052 A1, Sep. 1, 2022
Int. Cl. H01L 23/552 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A substrate structure, comprising:
an interconnection structure;
a first dielectric layer adjacent to the interconnection structure;
a second dielectric layer disposed between the interconnection structure and the first dielectric layer;
a first electronic component in the first dielectric layer, wherein the first electronic component has an active surface facing away from the interconnection structure and a backside surface opposite to the active surface; and
a first conductive via penetrating through the first dielectric layer and electrically connected with the interconnection structure,
wherein the first conductive via exceeds past the backside surface of the first electronic component,
wherein the backside surface of the first electronic component and a surface of the first dielectric layer are substantially coplanar, and
wherein the backside surface of the first electronic component and the surface of the first dielectric layer directly contact the second dielectric layer.