| CPC H01L 23/5329 (2013.01) [H01L 23/5226 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/251 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a PMOSFET region and an NMOSFET region, which are spaced apart from each other in a first direction on a substrate;
a first active pattern and a second active pattern provided on the PMOSFET region and the NMOSFET region, respectively;
a first channel pattern on the first active pattern;
a source/drain pattern electrically connected to the first channel pattern;
an active contact electrically connected to the source/drain pattern, the active contact comprising a first conductive pattern and a first barrier pattern enclosing a portion of a side surface and a bottom surface of the first conductive pattern;
a gate electrode extending in the first direction to cross the first channel pattern;
a gate contact electrically connected to the gate electrode;
an air gap provided on the first barrier pattern to be adjacent to the side surface of the first conductive pattern; and
a lower via provided on the active contact,
wherein the lower via is adjacent to the air gap in the first direction, and
the air gap is provided between the gate contact and the first conductive pattern.
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