| CPC H01L 23/5286 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 84/981 (2025.01)] | 20 Claims |

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1. A semiconductor device comprising:
a first backside power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region; and
a second backside power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, wherein
vertical side surfaces of the first backside power rail are tapered and a width of an upper horizontal surface of the first backside power rail is greater than a width of a lower horizontal surface of the first backside power rail, wherein
vertical side surfaces of the second backside power rail are tapered and a width of an upper horizontal surface of the second backside power rail is less than a width of a lower horizontal surface of the second backside power rail, wherein
the first backside power rail and the second backside power rail each comprise vertical side surfaces which taper in an opposite direction from each other.
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