US 12,469,780 B2
Integrated circuit structure with recessed self-aligned deep boundary via
Mohit Haran, Hillsboro, OR (US); Sukru Yemenicioglu, Portland, OR (US); Pratik Patel, Portland, OR (US); Charles H. Wallace, Portland, OR (US); Leonard P. Guler, Hillsboro, OR (US); Conor P. Puls, Portland, OR (US); Makram Abd El Qader, Hillsboro, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,779.
Prior Publication US 2023/0420360 A1, Dec. 28, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 84/90 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5283 (2013.01); H10D 84/907 (2025.01); H10D 89/10 (2025.01); H10D 84/975 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures;
a plurality of trench contacts extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and
a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure comprising a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.