US 12,469,779 B2
Semiconductor devices having a wiring provided with a protective layer
Kyounghee Kim, Hwaseong-si (KR); Jinsub Kim, Seoul (KR); Munjun Kim, Suwon-si (KR); and Junkwan Kim, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 26, 2022, as Appl. No. 17/729,131.
Claims priority of application No. 10-2021-0114025 (KR), filed on Aug. 27, 2021.
Prior Publication US 2023/0067987 A1, Mar. 2, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5283 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H10B 12/315 (2023.02); H10B 12/0335 (2023.02); H10B 12/50 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a lower structure including a device and a lower wiring structure;
an insulating layer disposed on the lower structure;
a via penetrating through the insulating layer;
a wiring pattern formed on the insulating layer and the via; and
a silicon oxide layer covering the wiring pattern, and including hydrogen,
wherein the wiring pattern includes a first conductive layer, a second conductive layer, an upper surface protective layer, and a side surface protective layer, wherein the second conductive layer is disposed on the first conductive layer, wherein the upper surface protective layer covers an upper surface of the second conductive layer, and the side surface protective layer covers a side surface of the first conductive layer and a side surface of the second conductive layer,
wherein each of the upper surface protective layer and the side surface protective layer includes a metal material having an activation energy higher than that of a metal material of the second conductive layer, and
wherein the wiring pattern further comprises an upper interfacial alloy layer disposed between the upper surface of the second conductive layer and the upper surface protective layer; and
a side interfacial alloy layer disposed between the side surface of the second conductive layer and the side surface protective layer;
a side interfacial alloy layer disposed between the side surface of the second conductive layer and the side surface protective layer.