US 12,469,777 B2
BEOL interconnect subtractive etch super via
Prasad Bhosale, Albany, NY (US); Nicholas Anthony Lanzillo, Wynantskill, NY (US); Lawrence A. Clevenger, Saratoga Springs, NY (US); and Michael Rizzolo, Delmar, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 7, 2021, as Appl. No. 17/543,964.
Prior Publication US 2023/0178474 A1, Jun. 8, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76807 (2013.01); H01L 21/76816 (2013.01); H01L 23/5283 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device including a super via connection between levels, comprising:
a first interlevel dielectric layer;
a back-end-of-line (BEOL) interconnect structure disposed in the first interlevel dielectric layer;
a second interlevel dielectric layer disposed on a first portion of the first interlevel dielectric layer;
a third interlevel dielectric layer disposed on the second interlevel dielectric layer; and
a super via disposed on a second portion of the first interlevel dielectric layer and in an interlayer dielectric via layer, wherein the super via is spaced apart from the second interlevel dielectric layer and the third interlevel dielectric layer and a first end of the super via is connected to the BEOL interconnect structures and wherein a second end of the super via opposite the first end of the super via is a distance from the first interlevel dielectric layer larger than a height distance of the second interlevel dielectric layer, and wherein the interlayer dielectric via layer is present at least along a sidewall of the second interlevel dielectric layer and the third interlevel dielectric layer.