US 12,469,776 B2
Semiconductor assembly comprising a 3D block and method of making the same
Timothy L. Olson, Phoenix, AZ (US); Craig Bishop, Scottsdale, AZ (US); Robin Davis, Vancouver, WA (US); and Paul R. Hoffman, San Diego, CA (US)
Assigned to Deca Technologies USA, Inc., Tempe, AZ (US)
Filed by Deca Technologies USA, Inc., Tempe, AZ (US)
Filed on Jan. 17, 2025, as Appl. No. 19/030,747.
Application 19/030,747 is a continuation of application No. 18/545,927, filed on Dec. 19, 2023, granted, now 12,205,881.
Claims priority of provisional application 63/435,185, filed on Dec. 23, 2022.
Prior Publication US 2025/0174542 A1, May 29, 2025
Int. Cl. H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/105 (2013.01); H01L 25/16 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/82005 (2013.01); H01L 2224/82106 (2013.01); H01L 2225/1035 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An assembly, comprising:
a 3D block, comprising:
a conductive element comprising conductive traces, the conductive element comprising a barrier layer disposed along a surface of each of the conductive traces, and
a support material disposed around the conductive element, wherein the support material comprises a cut or ground edge;
at least one component comprising conductive studs over a carrier and laterally offset from the 3D block;
encapsulant disposed over the carrier, around the 3D block, over and around the at least one component and around each of the conductive studs; and
a first interconnect structure formed over a surface of the encapsulant and coupled with the 3D block and the conductive studs.