US 12,469,768 B2
Semiconductor package structure and method for forming the same
Kuo Wen Chen, Hsinchu (TW); Hsiang-Tai Lu, Hsinchu County (TW); Chih-Hsuan Tai, Taipei (TW); and Ming-Chung Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Mar. 18, 2022, as Appl. No. 17/697,932.
Prior Publication US 2023/0298970 A1, Sep. 21, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10D 1/66 (2025.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 23/5223 (2013.01); H10D 1/66 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
receiving a substrate having a first surface and a second surface opposite to the first surface;
forming a barrier structure in the substrate near the first surface;
forming a capacitor in the substrate over the first surface, wherein a portion of the capacitor overlaps the barrier structure and separated from the barrier structure;
forming an interconnect structure over the first surface of the substrate, wherein the interconnect structure comprises a first via structure coupled to the substrate, and a second via structure coupled to the capacitor; and
forming at least a through via structure penetrating the substrate from the second surface to the first surface, wherein the through via structure is electrically connected to the interconnect structure.