US 12,469,767 B2
Integrated planar transistors and memory cell array architectures
Abhishek A. Sharma, Portland, OR (US); and Wilfred Gomes, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,413.
Prior Publication US 2023/0197571 A1, Jun. 22, 2023
Int. Cl. H01L 23/48 (2006.01); H10B 12/00 (2023.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 64/68 (2025.01)
CPC H01L 23/481 (2013.01) [H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01); H10D 64/514 (2025.01); H10D 64/683 (2025.01); H10D 64/691 (2025.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a planar transistor comprising a gallium nitride channel structure, a gate electrode, and a gate dielectric layer between the gallium nitride channel structure and the gate electrode, the gallium nitride channel structure having a band gap of not less than 3 eV;
a memory cell over and coupled to the planar transistor, the memory cell comprising a select transistor and a capacitor;
a plurality of first metallization layers between the planar transistor and the memory cell, the first metallization layers predominately comprising tungsten; and
a plurality second metallization layers over and laterally adjacent the memory cell, the second metallization layers predominately comprising a metal other than tungsten.