US 12,469,760 B2
Semiconductor structures and methods for manufacturing the same
Jui-Wen Su, Hsinchu (TW); Shi-Hua Tzeng, Hsinchu (TW); Chih-Hung Lu, Hsinchu (TW); and Po-Chi Wu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 27, 2023, as Appl. No. 18/140,553.
Prior Publication US 2024/0363467 A1, Oct. 31, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H10D 84/80 (2025.01)
CPC H01L 23/3171 (2013.01) [H01L 21/56 (2013.01); H01L 21/76804 (2013.01); H10D 84/811 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming a metal redistribution layer (RDL) within a via hole of a first passivation layer disposed over a wafer;
depositing a second passivation layer over a portion of the metal RDL;
depositing a polyimide layer over the second passivation layer;
performing an etching operation to form a first opening through the polyimide layer that exposes a first portion of the second passivation layer over the metal RDL;
performing a descum operation to adjust the first opening; and
etching the first portion of the second passivation layer exposed in the first opening to form a second opening to the metal RDL.