US 12,469,759 B2
Semiconductor package
Po-Han Wang, Hsinchu (TW); Hung-Jui Kuo, Hsinchu (TW); Yu-Hsiang Hu, Hsinchu (TW); and Sih-Hao Liao, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 25, 2022, as Appl. No. 17/994,004.
Application 17/994,004 is a division of application No. 16/667,854, filed on Oct. 29, 2019, granted, now 11,532,531.
Prior Publication US 2023/0089795 A1, Mar. 23, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/3128 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 25/16 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 24/94 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor die;
an encapsulant encapsulating the semiconductor die;
an electrical connector disposed over the encapsulant;
a redistribution conductive layer disposed over the semiconductor die and the encapsulant, wherein the redistribution conductive layer comprising a first conductive pad contacting the electrical connector and disposed between the encapsulant and the electrical connector;
a second conductive pad contacting the redistribution conductive layer;
a semiconductor component electrically connected to the second conductive pad, wherein the first conductive pad is located at lower height level than the second conductive pad,
a first inter-dielectric layer disposed over the semiconductor die and the redistribution conductive layer, wherein the first inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the first conductive pad and the electrical connector;
a second inter-dielectric layer and a third inter-dielectric layer disposed over the semiconductor die and under the first inter-dielectric layer;
a third conductive pad disposed on the second inter-dielectric layer and covered by the first inter-dielectric layer; and
a bridge structure inlaid within the second inter-dielectric layer, disposed on the third inter-dielectric layer, and connecting the first conductive pad and the third conductive pad, wherein the bridge structure comprises a first conductive via, a routing line and a second conductive via, the first conductive via directly connects the first conductive pad and the routing line, the routing line directly connects the first conductive via and the second conductive via, the second conductive via directly connects the routing line and the third conductive pad, and a whole bottom surface of the routing line is in direct contact with a top surface of the third inter-dielectric layer, the first conductive pad is electrically connected to the semiconductor die, the routing line has a first side surface, a second side surface, a third side surface and a fourth side surface, the first side surface opposes to the second side surface, the third side surface opposes to the fourth side surface, and the first side surface, the second side surface, the third side surface and the fourth side surface of the routing line are directly surrounded by the second inter-dielectric layer.