US 12,469,752 B2
Mid-manufacturing semiconductor wafer layer testing
Feng-Chien Hsieh, Pingtung County (TW); Kuo-Cheng Lee, Tainan (TW); Yun-Wei Cheng, Taipei (TW); Chun-Hao Lin, Tainan (TW); and Ting-Hao Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 7, 2023, as Appl. No. 18/230,664.
Application 18/230,664 is a division of application No. 17/463,556, filed on Sep. 1, 2021, granted, now 12,033,902.
Claims priority of provisional application 63/163,777, filed on Mar. 19, 2021.
Prior Publication US 2023/0402330 A1, Dec. 14, 2023
Int. Cl. H01L 21/66 (2006.01); H01L 21/265 (2006.01); H10F 39/10 (2025.01)
CPC H01L 22/20 (2013.01) [H01L 21/265 (2013.01); H01L 22/22 (2013.01); H01L 22/30 (2013.01); H10F 39/103 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a p-type substrate characterized by a first height in a vertical direction and comprising a circuit portion and a test portion;
a first deep p-well portion disposed in the circuit portion;
a second deep p-well portion disposed in the test portion;
a first cell p-well portion disposed in the circuit portion and extending from a top surface of the p-type substrate to a bottom surface of the first cell p-well portion, wherein the first deep p-well portion extends from the bottom surface of the first cell p-well portion to a bottom surface of the first deep p-well portion, and a distance between the top surface of the p-type substrate and the bottom surface of the first deep p-well portion is smaller than the first height; and
a second cell p-well portion disposed in the test portion and extending from the top surface of the p-type substrate to a bottom surface of the second cell p-well portion, wherein the second deep p-well portion extends from the bottom surface of the second cell p-well portion to a bottom surface of the second deep p-well portion, and a distance between the top surface of the p-type substrate and the bottom surface of the second deep p-well portion is smaller than the first height; and
wherein the second deep p-well portion and the second cell p-well portion are exposed, and wherein a first implantation profile of the second deep p-well portion in the test portion is a representation of a second implantation profile of the first deep p-well portion in the circuit portion, and a third implantation profile of the second cell p-well portion in the test portion is a representation of a fourth implantation profile of the first cell p-well portion in the circuit portion.