US 12,469,748 B2
CMOS-compatible graphene structures, interconnects and fabrication methods
Kaustav Banerjee, Goleta, CA (US); Junkai Jiang, Sunnyvale, CA (US); and Kunjesh Agashiwala, Santa Barbara, CA (US)
Assigned to The Regents of the University of California, Oakland, CA (US)
Appl. No. 18/252,459
Filed by The Regents of the University of California, Oakland, CA (US)
PCT Filed Dec. 1, 2021, PCT No. PCT/US2021/061361
§ 371(c)(1), (2) Date May 10, 2023,
PCT Pub. No. WO2022/140026, PCT Pub. Date Jun. 30, 2022.
Claims priority of provisional application 63/123,587, filed on Dec. 10, 2020.
Prior Publication US 2024/0014071 A1, Jan. 11, 2024
Int. Cl. H01L 21/768 (2006.01)
CPC H01L 21/76877 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76871 (2013.01)] 18 Claims
OG exemplary drawing
 
11. A method for forming MLG (multilayer graphene) on a metal surface, the method comprising:
forming an amorphous carbon barrier layer on the metal surface;
depositing a metal or metal alloy catalyst layer on the amorphous carbon barrier layer;
depositing a solid phase graphene precursor on the catalyst layer; and
diffusing carbon from the graphene precursor through the catalyst layer to deposit MLG on the metal surface via application of diffusion pressure at a diffusion temperature.