US 12,469,745 B2
Conductive structures with bottom-less barriers and liners
Shu-Cheng Chin, Hsinchu (TW); Ming-Yuan Gao, Hsinchu (TW); Chun-kai Chang, Hsinchu (TW); Chen-Yi Niu, Taipei (TW); Hsin-Ying Peng, Hsinchu (TW); Chi-Feng Lin, Hsinchu (TW); and Hung-Wen Su, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 25, 2022, as Appl. No. 17/652,593.
Claims priority of provisional application 63/203,767, filed on Jul. 30, 2021.
Prior Publication US 2023/0029867 A1, Feb. 2, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76844 (2013.01) [H01L 21/76807 (2013.01); H01L 21/7684 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a recessed portion in a dielectric layer above a first conductive structure;
depositing, selectively, a blocking layer at a bottom surface of the recessed portion;
depositing at least one barrier layer over sidewalls of the recessed portion, wherein the bottom surface of the recessed portion is substantially free of the at least one barrier layer;
removing the blocking layer;
depositing, after removing the blocking layer, at least one liner layer over the at least one barrier layer and over the bottom surface of the recessed portion, wherein the at least one liner layer is thinner at the bottom surface of the recessed portion than at the sidewalls of the recessed portion; and
forming a second conductive structure over the at least one liner layer in the recessed portion, wherein the second conductive structure is electrically connected to the first conductive structure through the at least one liner layer.