US 12,469,718 B2
Dense redistribution layers in semiconductor packages and methods of forming the same
Chen-Hua Yu, Hsinchu (TW); Hung-Jui Kuo, Hsinchu (TW); and Hui-Jung Tsai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 19, 2022, as Appl. No. 17/868,345.
Application 16/203,705 is a division of application No. 15/285,284, filed on Oct. 4, 2016, granted, now 10,340,206, issued on Jul. 2, 2019.
Application 17/868,345 is a continuation of application No. 16/203,705, filed on Nov. 29, 2018, granted, now 11,417,604.
Claims priority of provisional application 62/371,620, filed on Aug. 5, 2016.
Prior Publication US 2022/0352086 A1, Nov. 3, 2022
Int. Cl. H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 21/027 (2006.01); H01L 21/441 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC H01L 21/4846 (2013.01) [H01L 23/3114 (2013.01); H01L 23/498 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); H01L 21/0274 (2013.01); H01L 21/441 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/76819 (2013.01); H01L 21/76885 (2013.01); H01L 23/49811 (2013.01); H01L 23/5384 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/20 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1531 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
adhering a first die to a first dielectric layer;
forming an insulating material over the first die, wherein the insulating material surrounds the first die;
forming a first redistribution structure over the insulating material and the first die, wherein forming the first redistribution structure comprises:
forming a conductive line over the insulating material and the first die, wherein the conductive line is homogeneous and comprises a first conductive material;
depositing a mask layer over the conductive line, the insulating material, and the first die;
patterning the mask layer to form an opening that exposes a sidewall and a top surface of the conductive line; and
plating the first conductive material in the opening to form a first via, wherein the first via is homogeneous, wherein a bottommost surface of the first via is lower than a topmost surface of the conductive line, and a topmost surface of the first via is higher than the topmost surface of the conductive line.