US 12,469,714 B2
Gateline mask design for removing sacrificial gateline polysilicon within stair step area
Beibei Li, Hubei (CN); Wei Xu, Hubei (CN); Bin Yuan, Hubei (CN); Zongke Xu, Hubei (CN); XiangNing Wang, Hubei (CN); and ZongLiang Huo, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Dec. 28, 2022, as Appl. No. 18/090,031.
Claims priority of application No. 202211511556.8 (CN), filed on Nov. 29, 2022.
Prior Publication US 2024/0178001 A1, May 30, 2024
Int. Cl. H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01)
CPC H01L 21/31144 (2013.01) [H01L 21/76877 (2013.01); H10B 41/20 (2023.02); H10B 43/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a stack of alternating word line layers and insulating layers, the stack including a core area and a stair step area connected to the core area;
one or more gate line (GL) structures through the word line layers and the insulating layers of the stack, the GL structures extending from the core area to the stair step area, at least one of the GL structures having a first width within the core area and a second width within the stair step area that is different from the first width;
one or more first channel structures formed through the stack within the core area; and
one or more stair step contacts (SCTs) each formed through at least a portion of the stack within the stair step area, the SCTs each connecting one of the word line layers of the stack within the stair step area.