US 12,469,709 B2
Semiconductor package electrical contact structures and related methods
Francis J. Carney, Mesa, AZ (US); Michael J. Seddon, Gilbert, AZ (US); Yusheng Lin, Phoenix, AZ (US); Takashi Noma, Ota (JP); and Eiji Kurose, Oizumi-machi (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Jun. 23, 2022, as Appl. No. 17/808,338.
Application 17/808,338 is a division of application No. 16/861,994, filed on Apr. 29, 2020, granted, now 11,393,692.
Application 16/702,958 is a division of application No. 15/679,661, filed on Aug. 17, 2017, granted, now 10,529,576, issued on Aug. 18, 2020.
Application 16/861,994 is a continuation in part of application No. 16/702,958, filed on Dec. 4, 2019, granted, now 11,328,930, issued on May 10, 2022.
Application 16/861,994 is a continuation in part of application No. 15/921,898, filed on Mar. 15, 2018, granted, now 10,748,850, issued on Jan. 7, 2020.
Prior Publication US 2022/0384204 A1, Dec. 1, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/302 (2006.01); H01L 21/3065 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/12 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01)
CPC H01L 21/302 (2013.01) [H01L 21/30655 (2013.01); H01L 21/48 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/12 (2013.01); H01L 23/295 (2013.01); H01L 23/3114 (2013.01); H01L 23/3185 (2013.01); H01L 24/03 (2013.01); H01L 24/04 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/26 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/05005 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13541 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/94 (2013.01); H01L 2924/182 (2013.01); H01L 2924/18301 (2013.01); H01L 2924/186 (2013.01); H01L 2924/30205 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/381 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor package, comprising:
providing a die comprising a first side and a second side;
forming a first layer of a first pad and a second pad on the first side of the die;
forming a second layer of the first pad and the second pad, the second layer thicker than the first layer;
forming a first conductor directly on the first pad;
forming a second conductor directly on the second pad;
applying an organic material to the first side of the die, sidewalls of the first pad, sidewalls of the second pad, sidewalls of the first conductor, and sidewalls of the second conductor;
forming a first contact layer over the first conductor; and
forming a second contact layer over the second conductor;
wherein a spacing between the first contact layer and the second contact layer is wider than a spacing between the second layer of the first pad and the second layer of the second pad.