US 12,469,702 B2
Methods of manufacturing semiconductor devices including a repeating pattern of lines and spaces
Seungkyo Lee, Suwon-si (KR); Jongin Kang, Suwon-si (KR); Gyeyoung Kim, Suwon-si (KR); Youngwoo Kim, Suwon-si (KR); Yonghan Park, Suwon-si (KR); Woojin Jung, Suwon-si (KR); Seunguk Han, Suwon-si (KR); and Juyoung Huh, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 19, 2023, as Appl. No. 18/136,407.
Claims priority of application No. 10-2022-0072567 (KR), filed on Jun. 15, 2022.
Prior Publication US 2023/0411157 A1, Dec. 21, 2023
Int. Cl. H01L 21/033 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 23/16 (2006.01); H01L 23/544 (2006.01)
CPC H01L 21/0337 (2013.01) [H01L 21/0228 (2013.01); H01L 21/0271 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/16 (2013.01); H01L 23/544 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate including a main chip region and a scribe lane region;
patterning the second mandrel layer to form second mandrel patterns that extend in a first direction and separated from each other on the main chip region and the scribe lane region;
forming first spacers on the second mandrel patterns in the main chip region and the scribe lane region;
removing the second mandrel patterns;
patterning the second separation layer and the first mandrel layer by using the first spacers to form first structures that include a first mandrel pattern and a second separation layer pattern stacked on the first mandrel pattern;
forming a second spacer layer on the first structures and on the first separation layer in the main chip region and the scribe lane region;
anisotropically etching the second spacer layer to form second spacers on side walls of the first structures of the main chip region, and to form first dummy patterns and align key patterns on the side walls of the first structures of the scribe lane region; and
spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.