US 12,469,698 B2
Wafer having silicon substrate with suppressed fractures, semiconductor device, and method for manufacturing the wafer
Jumpei Tajima, Mitaka (JP); Hajime Nago, Yokohama (JP); Toshiki Hikosaka, Kawasaki (JP); and Shinya Nunoue, Ichikawa (JP)
Assigned to KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP)
Filed on Aug. 10, 2022, as Appl. No. 17/884,631.
Claims priority of application No. 2021-205644 (JP), filed on Dec. 20, 2021.
Prior Publication US 2023/0197444 A1, Jun. 22, 2023
Int. Cl. H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/815 (2025.01); H10D 62/85 (2025.01); H10D 62/854 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01)
CPC H01L 21/02458 (2013.01) [H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A wafer, comprising:
a silicon substrate including a first surface; and
a nitride semiconductor layer provided on the first surface,
the silicon substrate including a plurality of first regions that can be distinguished from each other in an X-ray image of the wafer,
the plurality of first regions being separated from an outer edge region of the silicon substrate,
one of the plurality of first regions including a plurality of first linear bodies linearly extending along a first line direction, the first line direction corresponding to a first deviation direction of a crystal lattice of the one of the first regions,
an other one of the plurality of first regions including a plurality of second linear bodies along a second line direction, the second line direction corresponding to a second deviation direction of a crystal lattice of the other one of the first regions, and
the second line direction crossing the first line direction.