US 12,469,578 B2
Phase-change memory controller capable of reducing write power and phase-change memory system including same
Dong Sop Lee, Icheon-si (KR); and Tae Ho Lim, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 19, 2023, as Appl. No. 18/490,685.
Claims priority of application No. 10-2023-0044411 (KR), filed on Apr. 4, 2023.
Prior Publication US 2024/0339171 A1, Oct. 10, 2024
Int. Cl. G11C 29/52 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC G11C 29/52 (2013.01) [H03M 13/11 (2013.01); H03M 13/611 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A phase-change memory controller configured to control a phase-change memory device, comprising a write control circuit configured to 1) receive first write data to be written to the phase-change memory device and having a first number of bits, the first number being a natural number greater than 2, and 2) generate second write data including compressed data obtained by compressing the first write data to a second number of bits, the second number being a natural number smaller than the first number, the second write data further including padding data that has a size corresponding to a difference between the first number and the second number, and the padding data having a predetermined value, and
a read control circuit including a multiplexer, a decoder, and a decompression circuit,
wherein the multiplexer is configured to receive the first read data and parity data from the phase-change memory device through an input terminal, and to output the first read data and the parity data to a first output terminal or a second output terminal, based on a selection signal transmitted through a selection terminal,
wherein the decoder is configured to perform a decoding based on an error correction code on the first read data transmitted from the multiplexer,
wherein a decompression circuit is configured to perform decompressing on the first read data and generate second read data, and
wherein the first output terminal and the second output terminal of the multiplexer are coupled to the write control circuit and the decoder, respectively.