US 12,469,577 B2
Semiconductor system related to performing an error check scrub operation
Choung Ki Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 14, 2024, as Appl. No. 18/441,264.
Claims priority of application No. 10-2023-0139065 (KR), filed on Oct. 17, 2023.
Prior Publication US 2025/0125000 A1, Apr. 17, 2025
Int. Cl. G11C 11/00 (2006.01); G11C 8/06 (2006.01); G11C 8/18 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 8/06 (2013.01); G11C 8/18 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor system comprising:
a controller configured to output a chip selection signal and a command address including a first logic level combination for performing a read operation and configured to then output a chip selection signal and a command address including a second logic level combination different from the first logic level combination for performing an error check scrub (ECS) operation; and
a semiconductor device comprising a plurality of memory cells and configured to receive the command address to generate an internal command address used to generate a latch row address and a latch column address by latching the internal command address when an error occurs in internal data that is output from a memory cell that is selected, from the plurality of memory cells, after a start of the read operation based on the chip selection signal and the command address, configured to determine a priority of the ECS operation for the plurality of memory cells corresponding to the latch row address and the latch column address, and configured to store the internal data in the same memory cell again that was selected after correcting the error of the internal data.