US 12,469,576 B2
Memory with arrays of sense amplifiers and two error checking and correction (ECC) modules
Weibing Shang, Hefei (CN); Yicheng Gao, Hefei (CN); and Hangtian Ba, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 2, 2023, as Appl. No. 18/364,060.
Application 18/364,060 is a continuation of application No. PCT/CN2022/123944, filed on Oct. 9, 2022.
Claims priority of application No. 202211013658.7 (CN), filed on Aug. 23, 2022.
Prior Publication US 2024/0071555 A1, Feb. 29, 2024
Int. Cl. G11C 29/52 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 7/12 (2013.01); G11C 7/18 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory, comprising:
memory sections and a plurality of bit lines (BLs) corresponding to a same memory section;
sense amplifiers, electrically connected to the plurality of BLs in one-to-one correspondence, wherein two of the sense amplifiers corresponding to adjacent two of the BLs are located on two sides of the memory section; and
a first error checking and correction (ECC) module and a second ECC module, wherein one of two adjacent sense amplifiers located on a same side of the memory section is electrically connected to the first ECC module, and the other one of the two adjacent sense amplifiers located on the same side of the memory section is electrically connected to the second ECC module;
wherein the memory section has a first side and a second side opposite to each other, a region in which the sense amplifiers being in the first side are located comprises a first region and a second region, and a region in which the sense amplifiers being in the second side are located comprises a third region and a fourth region, wherein the first region directly faces the third region, and the second region directly faces the fourth region; and the memory further comprises: a first BL selection module and a second BL selection module, wherein
the BLs corresponding to the sense amplifiers in the first region and the fourth region are controlled to be turned on by the first BL selection module, the BLs corresponding to the sense amplifiers in the second region and the third region are controlled to be turned on by the second BL selection module, and one of the first BL selection module and the second BL selection module is enabled.