US 12,469,574 B2
Methods for recovery for memory systems and memory systems employing the same
Rachael Skreen, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 16, 2024, as Appl. No. 18/444,176.
Application 18/444,176 is a continuation of application No. 17/571,319, filed on Jan. 7, 2022, granted, now 11,929,133.
Prior Publication US 2024/0185941 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 29/1201 (2013.01); G11C 29/12015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a controller;
a plurality of semiconductor devices operably connected to the controller;
circuitry configured to measure a performance metric for each semiconductor device of the plurality; and
circuitry configured to select, based upon the measured performance metric, a subset of the semiconductor devices of the plurality to disable in response to a recovery command.