US 12,469,570 B2
Memory device and method of operating the same
Chan Hui Jeong, Gyeonggi-do (KR); Dong Hun Kwak, Gyeonggi-do (KR); and Se Chun Park, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 17, 2023, as Appl. No. 18/318,725.
Claims priority of application No. 10-2022-0159091 (KR), filed on Nov. 24, 2022.
Prior Publication US 2024/0177785 A1, May 30, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0433 (2013.01); G11C 16/102 (2013.01); G11C 16/14 (2013.01); G11C 16/32 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells;
a peripheral circuit configured to perform a fail bit detection operation on memory cells selected from among the plurality of memory cells; and
a control logic configured to:
a) for the fail bit detection operation, compare a cell current flowing through a bit line of the memory cells with a reference current flowing in the control logic,
b) control the peripheral circuit to set target parameters related to a main operation of the memory device based on a comparison result between a fail bit detection time measured in the fail bit detection operation when the cell current exceeds the reference current and a reference time comprising a time period between turning a page buffer on and turning the page buffer off, wherein the comparison result comprises a difference value indicating a deterioration of the memory cells over time, and
c) perform the main operation on the selected memory cells based on adjustments of the target parameters made in accordance with the difference value.